Digital Soft-Start PSM Buck Converter

Although a typical PWM controller is well known for its good regulation capabilities, inrush current and overshoot voltage during start-up period as well as high switching losses at low loads are some of the major factors affecting its otherwise good performance. Therefore in this paper a simple Soft-start pulse skipping modulation (SSPSM) scheme implemented on a typical buck converter is presented to deal with the above mentioned problems. A soft-start scheme was designed to prevent the instantaneous rise of Vref from zero to full value and this was combined with a Pulse Skipping Modulation (PSM) logic circuit to reduce the switching losses at low loads. The proposed SSPSM buck converter was modeled and simulated in Matlab Simulink and the results clearly shows that the circuit was able to elongate the rise of Vref from zero to its maximum value thereby effectively eliminating inrush current and overshoot voltage. During steady state at low loads the circuit was shown to be able to skip some pulses thereby keeping the converter switch off for longer periods hence reducing the frequency of opening and closing of the switch.